This invention relates in general to phase-locked loops. More specifically, this invention relates to phase-locked loops wherein the loop is locked to a multiple of a reference oscillator frequency.
Phase-locked loops have become widely utilized in communication apparatus. They find specific application as frequency synthesizers and demodulators in transmitters and receivers.
Referring to FIG. 1, there is shown a block diagram of a conventional phase-locked loop. The conventional phase-locked loop includes a voltage controlled oscillator (VCO) 20, having a frequency of oscillation that is related to the magnitude of a VCO control signal applied to a control input 28 thereof. Voltage controlled oscillator 20 includes a high power output 30 serving as the phase-locked loop output and a lower power output 32. Low power output 32 provides a signal of the same frequency and phase as that provided by high power output 32 and is coupled through a divider 22 having a divide ratio N. The output of divider 22 is coupled to one of two signal inputs of a phase detector 24. The second signal input of phase detector 24 is coupled to the output of a reference source 26. The output frequency, F.sub.REF, of reference source 26 is fixed, predetermined, and stable. Phase detector 24 provides at its output a signal corresponding to the phase difference between the signals applied to its two signal inputs. Thus, the output of phase detector 24 corresponds to the instantaneous difference in phase between the signal from the output of divider 22 and the signal from the output of reference source 26. The output of phase detector 24 is filtered by a loop filter 27, generally having a low pass characteristic. The filtered signal provided by loop filter 27 becomes the VCO control signal for the phase-locked loop and is coupled to control input 28 of voltage controlled oscillator 20. The loop output signal, taken from output 30 of voltage controlled oscillator 20, has a frequency F.sub.OUT, where F.sub.OUT =N.multidot.F.sub.REF.
In the conventional phase-locked loop system, as illustrated in FIG. 1, voltage controlled oscillator 20 becomes locked to N times the frequency of reference source 26. Theoretically, with appropriate selection of the frequency F.sub.REF of reference source 20, the loop filter 26 characteristic, the divide ratio N and the center frequency of voltage controlled oscillator 20, a loop could be designed to lock onto any desired frequency. However, as phase-locked loop systems are applied to the design of communications equipment operating at higher frequencies, particularly in the UHF range, it becomes more and more difficult to provide practical divider circuits that function effectively.
Conventional digital dividers are based upon powers of two and it is not commercially feasible to create odd power multiples. This problem alone severely limits their application.
Also, most digital dividers are packaged in dual in line packages which do not lend themselves to hybrid circuit construction. Furthermore, binary dividers are quite expensive and have a high current drain.